This invention relates to memory bit corruption and, more particularly, to detecting memory bit corruption in integrated circuits.
Integrated circuits often contain memory elements. Typical memory elements are based on cross-coupled inverters (latches) and are used to store data. Each memory element can store a single bit of data.
Memory elements are often used to store configuration data in integrated circuits. For example, memory elements may be used to store configuration data in programmable logic device integrated circuits. Programmable logic devices are a type of integrated circuit that can be customized in relatively small batches to implement a desired logic design. In a typical scenario, a programmable logic device manufacturer designs and manufactures un-customized programmable logic device integrated circuits in advance. Later, a logic designer uses a logic design system to design a custom logic circuit.
The logic design system uses information on the hardware capabilities of the manufacturer's programmable logic devices to help the designer implement the logic circuit using the resources available on a given programmable logic device.
The logic design system creates configuration data based on the logic designer's custom design. When the configuration data is loaded into the memory elements of one of the programmable logic devices, it programs the logic of that programmable logic device so that the programmable logic device implements the designer's logic circuit.
Integrated circuits such as programmable logic devices are subject to a phenomenon known as single event upset (SEU). A single event upset is a change of state caused by ions or electro-magnetic radiation. Cosmic rays or radioactive impurities embedded in integrated circuits and their packages may be responsible for generating such ions or electro-magnetic radiation.
When ions or electro-magnetic radiation strike the silicon substrate on which the integrated circuit is implemented, electron-hole pairs are generated. The electron-hole pairs create a conduction path that can cause a charged node for example a memory element to discharge. Thus, a single event upset may cause a logic “1” in the memory element to chance to a logic “0”.
Upset events in sequential elements (e.g., memory elements, latches, or registers) can have serious repercussions and various error detection techniques have been examined and implemented in modern integrated circuits to address this issue. Typically, error detection techniques involve comparing the state of the sequential elements to their original state, and restoring them to the original state if a memory bit has been corrupted. However, such error detection techniques may not be applied instantaneously, and therefore there may be a risk that an integrated circuit operates with corrupted memory bits for at least some duration of time.